TSAT-PCI:

Features
 ●GPS Synchronized Timecode Generator
●GPS, IRIG-A, IRIG-B, and NASA36 timecode reader
●IRIG-B Output
●Time-Tag Input
●Programmable Periodic Output (pulse/squarewave) and Interrupt
●Programmable Start/Stop Time Output and Interrupt

The TSAT-PCI is a complete system package including the GPS Receiver/Antenna
(housed in a common enclosure), and a circuit card assembly for the PCI bus.
The board synchronizes its on-board clock to Coordinated Universal Time (UTC).
Other features include a time-tag TTL input, a programmable "heartbeat" pulse
or squarewave output (with interrupt capability), and a programmable "match"
start/stop time output (with interrupt capability).
The board continues to increment time ("freewheel") in the unlikely event that
reception of the satellite signals is lost. When the signals are re-established the
board automatically resumes synchronization.
The GPS satellites provide Coordinated Universal Time (UTC) accurate to within
one microsecond. A programmable time offset allows for compensation for
cable delays. They also provide position (longitude, latitude, and elevation).

 

TPRO-PCI Synchronizable Timecode Generator Specifcations

GPS Receiver/Antenna

Number of Satellites

6

Acquisition Time

(cold start)

5 minutes type, 15 min max

Re-acquisition Time

< 1 minute

Frequency

1575 Mhz (receive only) (L1 band, C/A code {SPS})

Sync to UTC

Within ± 1.0 µS max (antenna in stationary position)

Position

25 m SEP (w/o SA) (82 feet)

Altitude

0 m to +18,000 m (0 to +59,055 feet)

Size

147 mm Dia, 100 mm H (5.8” Dia, 3.9” H)

Pole Mount

1.00” I.D., 14 tuns/inch straight (not tapered)

Operating Temp

-30 to +70 C (-22 to +158 F)

Storage Temp

-55 to +100 C (-67 to +212 F)

Waterproof

Submersion to 1 m

Salt Fog

MIL-STD-202F, Method 101D Condition B

IRIG-B Output

Code Format

IRIG-B (B122)

Amplitude (mark)

2.5 Vp-p min, 3.3 Vp-p max

Modulation Ratio

3:1

Output Impedance

600 ohms

Time-Tag Input

Input Voltage

-0.5V min, +0.8V max for logic 0
+2.0V min, +5.5 max for logic 1
Tags rising edge

Input Current

<5 µA for logic 0
<5 µA for logic 1

Rise/Fall Time

500 nS max

Repetition Rate

200 events per second max

Timing Resolution

1 µS

Match Output

Output Voltage

3.8 V min at 6 mA (high)
0.4 V max at –6 mA (low)

Settability

1 µS

On-Board Clock

Resolution

1 µS

Range

366:23:59:59.999999

Date Format

Integer (001-366)

Cable Delay Correction

-1000 µS through +8999 µS (1 µS resolution)

Cable Delay Setting

Programmable

Open Loop Drift (no timecode input)

<2 µS in 10 seconds (2E-07) after operating with valid timecode input for 60 minutes

PCI Interface

Interface

PCI Spec. 2.1 compliant

I/O

64 bytes

DMA Transfers

None

General—Antenna Cable

Length

30.5 m ±0.2 m (100’ ±8”)

Maximum Length

92 m (300 feet)

Cable Size

9mm (0.35 inch) O.D.

Connector Size

20 mm (0.79”) O.D. (antenna end)
46mm (1.80”) O.D. (board end and extension cable)

Heartbeat Output

Output Voltage

3.8 V min at 6 mA (high) 0.4 V max at –6 mA (low)

Wave Shape

Pulse or Squarewave (programmable)

Pulse Width

150 nS min, 450 nS max

Pulse Polarity

Positive

Squarewave

45% - 55%

Timing

Rising edge on-time (pulse or squarewave)

Range

1.000 µS – 21.845 mS in 1 µS steps (1 MHz – 45.7771 Hz)

Power-on default Rate

100 PPS (pulse)